Advanced Computer Architectures by Unknown

Author:Unknown
Language: eng
Format: epub

170

Advanced Computer Architectures

corresponding to these instructions that are utilized by the PEs. Control

instructions are executed by the CP itself. The CP performs all the address

computations and might also retrieve some data elements from the memory

and broadcast them to all the PEs as required. This method of data distribution

can be employed when either a PE interconnection network is not available or

broadcasting is more efficient than using the PE interconnection network. The

CP is thus equivalent to an SISD processor except that the arithmetic/logic

functions are not performed by it.

5.1.3

Arithmetic/Logic Processors

The PEs perform the arithmetic and logical operations on the data. Thus each

PE corresponds to data paths and arithmetic/logic units (ALUs) of an SISD

processor, capable of responding to control signals from the control unit.

5.1.4

Interconnection Network

Figure 5.2 shows three top level models for SIMD architectures (Skillicorn, 1985). The Instruction processor (IP) in these models is the same as the CP

in the SIMD model of Chapter 2, and the Data Processor (DP) is same as the PE. All models have a 1-to- n switch connecting the single IP with n

DPs. In Figure 5.2(a) there is a single memory hierarchy (i.e., common data and instruction memory (IM)). There is a 1-to- n switch between the IP and

the memory hierarchy, and the DP to memory switch is n-to- n. The DPs

are connected by an n-by- n switch. This corresponds to the SIMD model

of Figure 2.5, which also depicts the structure of ILLIAC-IV. The DPs in ILLIAC-IV are actually connected by a torus, or mesh network in which

there is no n-by- n physical interconnection. But it is possible to exchange data between all the n DPs by repeated use of the interconnection network,

and hence, itis an n-by- n switch. In Figure 5.2(b) and 5.2(c), separate IM and data memory (DM) hierarchies are shown. The IP to IM interconnection is

thus 1-to-1.

In Figure 5.2(b), the DP interconnections are n-by- n and the DP to DM interconnections are n-to- n. This model depicts the structure of Thinking Machine Corporation’s CM. The CM uses a hypercube network between the DPs. It

is notphysically an n-by- n interconnection scheme but allows data exchange between all n DPs by repeated use of the network and hence logically is an

n-by- n switch.

In Figure 5.2(c), there is no direct connection between DPs and the interconnection between DM and DPs is n-by- n. This model depicts the structure of Burroughs Scientific Processor (BSP). The DP–DM switch in BSP is known as a

data alignment network because it allows each DP to be connected to its data

stream by dynamically changing the switch settings. Note that if the DP–DM

switch is n-to- n, as in Figure 5.2(a) and 5.2(b), data has to be moved into appropriate memory elements to allow access from the corresponding DP.

Array Processors

171

n × n

(a)

SW

1: n

SW

DP

IP

n : n

SW

1: n

Data

memory

hierarchy

(b)

n × n

1: n

SW

SW

DP

IP

n : n

SW

1: n

Instruction

memory

Data

hierarchy

memory

hierarchy

(c)

n × n

SW

1: n

SW

DP

IP

SW

1: n

Instruction

memory

hierarchy

Data

memory

hierarchy

FIGURE 5.2

SIMD models (Skillicorn, 1985): (a) Type 1, (b) Type 2, and (c) Type 3 (Reproduced from IEEE.

With permission.)

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