Asynchronous Circuit Applications by Jia Di;Scott C. Smith;

Author:Jia Di;Scott C. Smith; [Неизв.]
Language: eng
Format: epub
ISBN: 9781785618178
Publisher: Institution of Engineering & Technology
Published: 2019-12-17T21:00:00+00:00

Figure 8.2 Mesochronous MPSoC: (a) shows the distribution within the NoC and (b) shows the potential corresponding clock trees and the phase shift of the clocks

Furthermore, in [6] the potential to reduce power dissipation is shown. By implementing a NoC as a GALS system, it is possible to dynamically adapt individual synchronous modules to current performance requirements. This allows nodes with lower performance requirements to be operated at a lower clock frequency. As a result the supply voltage can be adjusted during runtime as well, which is also known as dynamic voltage and frequency scaling (DVFS) [7]. The system is partitioned into several blocks (also called voltage islands) with different supply voltages [8]. According to [9], both the adaptation of the clock frequency and the supply voltage result in a strong reduction of the power dissipation.

Since in a GALS system the different synchronous modules are asynchronous to each other, synchronization is required. This synchronization is necessary to prevent registers in a module to take metastable states.* If a signal arrives at the input register of a receive module, it cannot be guaranteed that the setup or hold times of the register are met. This can lead to a metastable state over an indefinite period of time.

When implementing an MPSoC as a GALS system, two different scenarios can be distinguished. The first scenario is the loosely synchronous system, in which a certain dependency between the different clocks is known at design time. This scenario can be divided into the mesochronous, plesiochronous, and heterochronous approaches. The second scenario is an asynchronous system in which modules are operated by completely different clocks [10].

However, improvements and the use of new design methods in modern tool flows also offer new possibilities for scaling synchronous architectures. Modern design tools offer the so-called clock concurrent optimization (CCOpt) design flow, in which clock tree and combinatorial logic are optimized simultaneously [11]. This makes it possible to use the phase shift of the clock (useful skew) to achieve higher clock frequencies. Nevertheless, GALS methods still allow for a higher resource efficiency because they are almost completely independent of any phase shift. A comparison of the new CCOpt design process with different GALS methods is shown in Section 8.2.5.

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