Quick Guide to Digital Design using VHDL by Dr. Amol Deshmukh & Chakradhar Borkute & Chetna Kharkar

Author:Dr. Amol Deshmukh & Chakradhar Borkute & Chetna Kharkar [Deshmukh, Dr. Amol]
Language: eng
Format: mobi
Published: 2020-04-11T00:00:00+00:00

Input output blocks (IOB).

These blocks provide buffering for devices inputs & outputs from external interfaces.

The datasheets indicate the devices names using following nomenclature XC9536PC44 where XC95 => Devices series,

36=> number of macro cells, PC => PLCC package, 44=> number of pins.

Details of function Block:

Each FB is comprised of 18 macrocells, each capable of implementing combinational & registered function. Logic within the FB is implemented using sum-of-product representation.

Details of Macrocell:

​In a macrocell five direct product terms (each of maximum 36 variables) are available for use as primary data inputs to implement combinational functions, or as control inputs along clock, set/reset and output enable. The final OR gate which performs the summing operation has 5 inputs as direct product terms & one input that can provide the combination of SOP terms from rest of the macrocells within block.

​The register can be configured as a D/T flip-flop. Each register Support both synchronous set and reset operations. The set & reset lines are controlled either by the global signals or the product terms local to that macrocell. All global control signals are available to each individual macrocell.

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