Parallel Power Electronics Filters in Three-Phase Four-Wire Systems by Man-Chung Wong Ning-Yi Dai & Chi-Seng Lam

Author:Man-Chung Wong, Ning-Yi Dai & Chi-Seng Lam
Language: eng
Format: epub
Publisher: Springer Singapore, Singapore

(3.112)

where F is the input frequency of the external clock and r d is the scaling ratio.

3.5.3 Experimental Verification of the 3D PW Modulator

Prototypes for a two-level center-split VSI, a two-level four-leg VSI and a three-level center-split VSI were built. The FPGA-based generalized PW modulator was applied to control these VSIs to track the given references. The block diagram for the control system is shown in Fig. 3.79. A DSP (TMS320F2407) was used to generate the reference voltages and send the references to the data buffers in FPGA.

Fig. 3.79Block diagram for the control system

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