VLSI DESIGN SUBSYSTEM DESIGN PROCESSES AND ILLUSTRATION by Chaudhari Kiran

Author:Chaudhari, Kiran [Chaudhari, Kiran]
Language: eng
Format: epub, mobi, azw3
Publisher: UNKNOWN
Published: 2021-08-20T16:00:00+00:00

• Adder Enhancement Techniques:

– Carry skip adders:

• Adder Enhancement Techniques:

– Carry skip adders:

Figure 6.28: Carry skip adder structure (24-bit)

• Adder Enhancement Techniques: – Carry skip adders:

Optimization of the carry skip adder:

• Let us formalize that the total adder is made of N adder cells. It contains M blocks of P adder cells. The total of adder cells is thenN = M.P

• The time T needed by the carry signal to propagate through P adder cells is

T = k1 .P

• The time T' needed by the carry signal to skip through M adder blocks is

T‘ = k2 .M

• The problem to solve is to minimize the worst case delay which is: Tworst = 2(P– 1).k1 + (M– 2)

where P = n/M

• T is minimum when M = (2n.k1 /k2 )1/2

• Adder Enhancement Techniques:

– Carry skip adders:

Optimization of the carry skip adder:

Figure 6.29: Worst case carry propagation carry skip adder

• Adder Enhancement Techniques:

– Carry skip adders:

Optimization of the carry skip adder:

Figure 6.30: Block propagation carry skip adder

• Adder Enhancement Techniques:

– Carry look-ahead (CLA) adders:

Figure 6.31: Carry look-ahead adder structure

• Adder Enhancement Techniques:

– Carry look-ahead (CLA) adders:

Figure 6.32: Carry look-ahead and ripple through compromise

• Adder Enhancement Techniques:

– Carry look-ahead (CLA) adders:

Figure 6.33: 4-bit Carry look-ahead adder unit

• Adder Enhancement Techniques:

– Carry look-ahead (CLA) adders:

Figure 6.34: 16-bit, 4X4 block Carry look-ahead adder unit

• Adder Enhancement Techniques:

– Carry look-ahead (CLA) adders:

Figure 6.35: Generation of carry out (from 4-bits and carry in)

• Adder Enhancement Techniques:

– Carry look-ahead (CLA) adders:

Figure 6.36: Four-cell Manchester carry-chain

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