Digital System Design with FPGA: Implementation Using Verilog and VHDL (Electronics) by Cem Unsalan & Bora Tar

Digital System Design with FPGA: Implementation Using Verilog and VHDL (Electronics) by Cem Unsalan & Bora Tar

Author:Cem Unsalan & Bora Tar [Unsalan, Cem]
Language: eng
Format: epub, azw3, mobi
Publisher: McGraw-Hill Education
Published: 2017-07-13T22:00:00+00:00


Listing 8.27 Verilog Description of the Seven-Segment Display Decoder Module

We provide the modified Verilog description for the application in Listing 8.29. Here, the home alarm system in Listing 7.5 is taken as an IP block. Therefore, we assume that the reader has converted it to an IP block and added it to the project.

8.7.3 Improving the Car Park Occupied Slot Counting System

We can improve the car park occupied slot counting system in two ways. First, we can extend the number of slots to be examined to nine. We provide the modified Verilog description for the car park occupied slot counting system in Listing 8.30. We should form an IP block for this part to be used in the project.

Second, we can display the number of occupied slots on the rightmost seven-segment display of the Basys3 board. To do so, we should add the seven-segment display decoder module in Listing 8.27. Based on these modifications, the Verilog description of the top module for car park occupied slot counting system will be as in Listing 8.31.

Listing 8.28 VHDL Description of the Seven-Segment Display Decoder Module



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