Analog Circuit Simulators for Integrated Circuit Designers by Mikael Sahrling

Author:Mikael Sahrling
Language: eng
Format: epub
ISBN: 9783030642068
Publisher: Springer International Publishing

for all the voltage nodes. If this max is >0.9, we step down a percentage; if it is <0.1, we step up another percentage; and if it is between these limits, we leave the timestep unchanged. This will keep the timesteps the same for large stretch of the simulation and should improve the accuracy. Let us implement this as in the following code snippet:

Let us run the oscillator for different reltols like we just did for the two-level algorithm. We find the result in Table 5.12.Table 5.12Three-level timestep adjustment algorithm as a function of reltol

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