Practical Analog and RF Electronics by Daniel B. Talbot

Author:Daniel B. Talbot
Language: eng
Format: epub, pdf
Publisher: CRC Press

In awhile we will introduce the (b) approach using familiar components to an RF designer and which offers the best performance up to arbitrarily high frequencies.

8.7.1 Tank Circuit Definitions

Refer to the resistance/inductance/capacitance (RLC) tank circuit shown in Figure 8.16. The circuit defines a second order bandpass filter, and any equivalent active realization can be transformed to this RLC model. The 3dB bandwidth is defined as

FIGURE 8.16

RLC tank circuit. (8.1)

where

BW = 3 dB bandwidth in Hz

R = tank parallel resistance in Ohms

C = tank capacitance in Farads

L = tank inductance in Henries

The tank resonant frequency is given by:

(8.2)

where

fR = tank resonant frequency in Hz

L = tank inductance in Henries

C = tank capacitance in Farads

Then, we define Q as:

(8.3)

Remember that for any we have (i.e., Hz and radians per second are related by 2π).

The phase angle of this tank is given in radians as:

(8.4)

And the group delay in seconds for this second order equalizer stage is:

(8.5)

Or by taking that derivative,

(8.6)

So, for Figure 8.16 to become part of a second order allpass group delay equalizer with L = 100nH, and C = 100pF, and R = 1K ohms, the circuit must have the form of [(2 EOUT) − V1]. The actual allpass circuit is given in Figure 8.17 and the resultant phase and delay is graphed in Figure 8.18.

FIGURE 8.17

RLC tank circuit based second order delay EQ. FIGURE 8.18

Actual delay for the equalizer stage values shown. We check our equation next (it must agree with the simulated answers). For our example, using the values for R, L, and C,

= 3.16e8

And setting

GD at delay peak = 127/3.16e8 = 400 nsec

Success! The computed delay agrees with the simulated result.

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