ESD Design for Analog Circuits by Vladislav A. Vashchenko & Andrei Shibkov

Author:Vladislav A. Vashchenko & Andrei Shibkov
Language: eng
Format: epub
Publisher: Springer US, Boston, MA

4.8.3 Example 4.3 Two-Stage ESD Protection with Snapback NMOS

Library Name: Examples4_Snapback_Clamps

Project Name: E4.3_5 V_Two_stage_HNMOS_HBM

This example demonstrates the two-stage clamp ESD protection principle. The example is composed of a grounded gate snapback NMOS clamp, second stage resistor, and 7 V avalanche diode. Waveforms at different circuit nodes are compared for different avalanche diode breakdown voltages and the second stage resistor values (Fig. E4.3), demonstrating reduced overstress of the internal input node that is connected to the avalanche diode. Voltage overshoot reduction is important for CDM ESD pulse events.

Fig. E4.3Mixed-mode simulation circuit and comparison of the 2 kV HBM waveforms at the external and internal input nodes

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