ti :: TMS9900 :: TMS9995 by Unknown

Author:Unknown
Language: eng
Format: epub

NOTES: CRU INPUT.

© Valid Address SUCCESSIVE BITS.

IT NO WAITS

@ D0-D7 each output logic zero

@ Non-specific output bit

@ CRU input bit must be valid on CRUIN at CLKOUT edge indicated

CRU INPUT,

SINGLE BtT,

ONE WAIT STATE

FIGURE 20 - TMS9995 CRU INPUT CYCLE

To output a data bit to an extern a! (off-c hip) CRU device, the TMS 9995 first outputs the appropriate address on A0-A14. The TMS 99 95 leaves MEM EN high, outputs logic zeroes on D0-D2, outputs the data bit on A15/ CRUOUT, and strobes WE/CRUCLK. Completion of each CRU output cycle and/or generation of Wait states is determined by the READY input as detailed in Section 2.3.1.3. Timing relationships of the CRU output cycle are shown in Figure 21.

For multiple-bit transfers, these input and output cycles are repeated until transfer of the entire field of data bits specified by the CRU instruction being executed has been accomplished.

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