Radiation Hardened CMOS Integrated Circuits for Time-Based Signal Processing by Jeffrey Prinzie Michiel Steyaert & Paul Leroux

Author:Jeffrey Prinzie, Michiel Steyaert & Paul Leroux
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

The dynamic range of the TDC can be extended with a counter which runs at the reference clock since the VCDL can only represent the timing information that is limited within 1 cycle. To improve the linearity and noise of the DLL, a high speed reference clock is required [122]. High clock speeds place serious constraints on the digital counters, especially if a TMR structure is required which limits the speed to 1 GHz or slightly above in 65 or 40 nm CMOS technologies. The counter’s value is sampled in a similar way as the VCDL is sampled when a hit signal arrives. However, the timing information in the counter and VCDL is encoded in a different way. The VCDL has a pseudo thermometric coding. Since the hit signal is asynchronous, it may introduce metastability in flip-flops where setup or hold times are violated. In the pseudo thermometric code this may result in 1 LSB error when the hit signal arrives at the edge of a bin. The counters typically encode the count value in a binary fashion. Furthermore, the counters also represent the MSB information of the timed signals. Any errors in this data will result in significant malfunctions. When a counter changes its value after the rising edge of the clock, the output bits are unstable for some period of time. If the hit signal samples the counter within this time frame, the result will be incorrect.

The dynamic range extension that uses two counters is shown in Fig. 4.13b. One counter counts at the rising edge of the high speed clock, which also drives the DLL, while the other counter counts at the falling edge of the clock. Upon arrival of a hit signal, both counters are sampled into an L0 register. The idea of this approach is that at least one counter will be stable at any point in time. Therefore, when the hit signal arrives, one of the counters will provide a stable value. In the first part of the clock cycle, CTR1 will not be stable. It can be assumed that the counter is unstable from the launching time of the clock until the propagation delay of the flip-flops in the counter. The delay of any clock-tree is not included here since the same clock delay is assumed in the DLL and hit tree to balance all clock paths. The counter should be stable within half the clock cycle of the reference clock of the DLL. Since CTR2 toggles at the falling edge, it will be unstable in the other half of the clock cycle. When the hit signal has sampled both counters, either CTR1 or CTR2 has to be chosen. This decision can be made with the MSB of the decoded values from the decoder from the VCDL. The decoded signal from the VCDL represents the time difference between the HIT signal and the reference clock. The MSB can therefore identify if the HIT occurred in the first, of second half of the period.

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