Novel Three-state Quantum Dot Gate Field Effect Transistor by Supriya Karmakar

Author:Supriya Karmakar
Language: eng
Format: epub
Publisher: Springer India, New Delhi

5.3 QDNMOS Inverter

5.3.1 Device Structure

Figure 5.2 shows the cross-sectional schematic of the QDNMOS inverter [9]. Here, an n-type source and drain are used in a p-silicon (100) substrate. The gate consists of a thin layer of tunneling oxide followed by two layers of SiOx-Si-cladded quantum dots [10–14].

Fig. 5.2Cross-sectional schematic of QDNMOS inverter [9]

Figure 5.3 shows the topology of the fabricated device. Here, A is the top transistor where the drain and the gate are connected by metal contact. The output terminal, VOUT, is the source for the top transistor as well as the drain for the bottom transistor (B). The input terminal, VIN, is the gate contact of bottom transistor (B), and the source of the bottom transistor (B) is connected to the ground.

Fig. 5.3Top view of fabricated QDNMOS inverter [9]

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