Machine Learning-based Design and Optimization of High-Speed Circuits by Vazgen Melikyan

Author:Vazgen Melikyan
Language: eng
Format: epub
ISBN: 9783031507144
Publisher: Springer Nature Switzerland

4.1.5 Causes of Nonlinearity Occurrence in Signal’s Analog-to-Digital Conversion and the Importance and Necessity of Its Reduction in Pipeline ADCs

Another very popular and widely used ADC in modern ICs is the pipeline ADC. It is mainly used in such functions, when the operating frequencies do not exceed 100 MHz. This ADC is slower compared to a flash ADC, but it has a clear advantage in terms of bits. In case of the same area its bit is greater. The simplest pipeline ADC consists of N cascades, each of which receives B bit. In order to obtain a B-bit signal, the input analog signal in each cascade is first selected and stored by a sample-hold (S/H) device, then exposed to coarse quantization (digitization) by means of a sub-range ADC (Fig. 4.13) [47]. The analog voltage is then restored by a sub-DAC, after which the quantized signal is subtracted from the input signal to yield the quantization error. To bring the quantization error to full-scale voltage range, the error is multiplied by 2B − 1 which is performed by OpAmp (Fig. 4.14) [47–50]. The obtained voltage is applied to the input of the next cascade, which has exactly the same structure. Timing and digital correction is done for the obtained B bits by a synchronization and digital error correction device, after which a Y-order digital output corresponding to the input analog signal is obtained.

Fig. 4.13Pipeline ADC block diagram

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