Learn Digital Electronics: Principles, Devices And Applications by Virender Singh

Author:Virender Singh [Singh, Virender]
Language: eng
Format: epub
Published: 2015-10-04T22:00:00+00:00

Figure 10.39 D flip-flop.

D J Q

Clk FF

K

Figure 10.40 J-K flip-flop as aD flip-flop.

Enable D Q

D-Input Enable FF

Q-Output

(a)

CLK D Q

D-Input FFClk

Q-Output

(b)

Figure 10.41 Comparison between aD-type latch and aD flip-flop. A D flip-flop should not be confused with aD latch. In aD flip-flop, the data on theD input are transferred to theQ output on the positive- or negative-going transition of the clock signal, depending upon the flip-flop, and this logic state is held at the output until we get the next effective clock transition. The difference between the two is further illustrated in Figs 10.41(a) and (b) depicting the functioning of aD latch and aD flip-flop respectively.

D

–

Q

Q

Enable

To-other D-Latches

Figure 10.42 Example 10.6.

Example 10.6 Figure 10.42 shows the internal logic circuit diagram of one of the four D latches of a four-bit D latch in IC 7475. (a) Give an argument to prove that the Q output will track the D input only when the ENABLE input is HIGH. (b) Also, prove that the Q output holds the value it had just before the ENABLE input went LOW during the time the ENABLE input is LOW.

Solution

(a) When the ENABLE input is HIGH, the upper AND gate is enabled while the lower AND gate is disabled. The outputs of the upper and lower AND gates areD and logic ‘0’ respectively. They constitute inputs of the NOR gate whose output isD . TheQ output is thereforeD.

(b) When the ENABLE input goes LOW, the upper AND gate is disabled (with its output going to logic ‘0’) and the lower AND gate is enabled (with its output becoming the same as theQ output owing to the feedback). The NOR gate output in this case isQ , which means that theQ output holds its state as long as the ENABLE input is LOW.

10.8 Synchronous and Asynchronous Inputs Most flip-flops have both synchronous and asynchronous inputs. Synchronous inputs are those whose effect on the flip-flop output is synchronized with the clock input. R, S, J, K and D inputs are all synchronous inputs. Asynchronous inputs are those that operate independently of the synchronous inputs and the input clock signal. These are in fact override inputs as their status overrides the status of all synchronous inputs and also the clock input. They force the flip-flop output to go to a predefined state irrespective of the logic status of the synchronous inputs. PRESET and CLEAR inputs are examples of asynchronous inputs. When active, the PRESET and CLEAR inputs place the flip-flopQ output in the ‘1’ and ‘0’ state respectively. Usually, these are active LOW inputs. When it is desired that the flip-flop functions as per the status of its synchronous inputs, the asynchronous inputs are kept in their inactive state. Also, both asynchronous inputs, if available on a given flip-flop, are not made active simultaneously.

10.9 Flip-Flop Timing Parameters Certain timing parameters would be listed in the specification sheet of a flip-flop. Some of these parameters, as we will see in the paragraphs to follow, are specific to the logic family to which the flip-flop belongs.

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