FPGA-based Implementation of Signal Processing Systems by Woods Roger & McAllister John & Lightbody Gaye & Yi Ying

Author:Woods, Roger & McAllister, John & Lightbody, Gaye & Yi, Ying
Language: eng
Format: epub
ISBN: 9781119077961
Publisher: Wiley
Published: 2017-02-14T00:00:00+00:00

7.6.3 GAUT

GAUT is an academic HLS tool (http://www.gaut.fr/) that has been targeted at DSP applications (Coussy et al. 2008). It allows the user to start from a C/C++ description of the algorithm and supports fixed-point representation to allow more efficient implementation on FPGAs. The user can set the throughput rate and the clock period as well as other features such as memory mapping (Corre et al. 2004) and I/O timing diagrams (Coussy et al. 2006). The tool synthesizes an architecture consisting of a processing unit, a memory unit and a communication and interface block. The processing unit is composed of logic and arithmetic operators, storage elements, steering logic and an FSM controller.

The flow for the tool is given in Figure 7.5. It starts with the design of the architecture, which involves selecting the arithmetic operators, then the memory registers and memory banks involving memory optimization, followed by the communication paths such as memory address generators and the communication interfaces. It generates not only VHDL models but also the testbenches and scripts necessary for the Modelsim simulator. It has been applied to a Viterbi decoder and a number of FIR and LMS filters, giving a reduction in code of around two orders of magnitude.

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