Electronics for Embedded Systems by Ahmet Bindal

Author:Ahmet Bindal
Language: eng
Format: epub, pdf
Publisher: Springer International Publishing, Cham

The middle table in Fig. 7.9 shows how the conversion takes place if the down-rounding mechanism is used in this four-bit ADC . Prior to its operation, the four-bit up-counter is reset and produces C[3:0] = 0000. Assuming an analog voltage of 2 V is applied to the input, which must be kept constant until the conversion is complete, C[3:0] = 0000 forces the DAC output, DACOUT, to be 0 V according to the down-rounding scheme. Since this value is less than 2 V at the sample/hold circuit output, SHOUT, the output of the differential amplifier, INCR, transitions to the positive supply potential of the operational amplifier, +VCC = 5 V, which prompts the four-bit counter to increment to C[3:0] = 0001. Consequently, the DAC generates DACOUT = 0.3125 V according to the truth table in Fig. 7.9. However, this value is still less than SHOUT = 2 V. Therefore, the differential amplifier produces another INCR = 5 V which prompts the counter to increment again to C[3:0] = 0010. Up-counting continues until C[3:0] = 0111 or DACOUT = 2.1875 V. Since this last voltage is greater than SHOUT = 2 V, the differential amplifier output switches back to its negative supply voltage, −VCC = 0 V, and stops the up-counter from incrementing further. The digital output stays steady at C[3:0] = 0111 from this point forward, representing 2 V analog voltage with a dynamic error of 0.1875 V.

The table at the bottom part of Fig. 7.9 represents the conversion steps if the up-rounding mechanism is used in this ADC . External reset still produces C[3:0] = 0000 initially. However, the DAC output starts the conversion with an increased amount of 0.3125 V instead of 0 V. The counter increments until C[3:0] = 0110, and produces 2.1875 V at the DACOUT node. At this value INCR becomes 0 V, and the up-counter stops incrementing further. C[3:0] = 0110 becomes the ADC result for 2 V.

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