Digital Design using VHDL: A Systems Approach by Dally William J. & Harting R. Curtis & Aamodt Tor M

Author:Dally, William J. & Harting, R. Curtis & Aamodt, Tor M.
Language: eng
Format: epub
Publisher: Cambridge University Press
Published: 2015-12-16T16:00:00+00:00

14.1Homing sequences, I. The finite-state machine described by Table 14.2 does not have a reset input. Explain how you can get the machine in a known state regardless of its initial starting state by providing a fixed input sequence. An input sequence that always takes an FSM to the same state is called a homing sequence.

14.2Homing sequences, II. Suppose the traffic-light controller FSM of Table 14.4 did not reset to state GNS. Find a homing sequence for the machine that will get it to state GNS.

14.3Modified traffic-light controller, I-I. Modify the traffic-light controller FSM of Table 14.4 so that it makes lights go red in both directions for one cycle before turning a light green. Show a state table and state diagram for your new FSM.

14.4Modified traffic-light controller, I-II. Choose a state assignment for the modified traffic-light controller of Exercise 14.3 and derive the logic to compute the next-state and output values. Show Karnaugh maps for the next-state variables and output variables and a gate-level schematic for the FSM.

14.5Modified traffic-light controller, I-III. Write and verify the VHDL that implements your state machine from Exercise 14.3.

14.6Modified traffic-light controller, II-I. Modify the traffic-light controller FSM of Table 14.4 so that it takes an additional input, carns, that indicates when there is a car waiting in the north–south direction. Change the logic so that, once the light has changed to east–west, it stays with east–west green until a car waiting in the north–south direction is detected. Show a state table and state diagram for your new FSM.

14.7Modified traffic-light controller, II-II. Choose a state assignment for the modified traffic-light controller of Exercise 14.6 and derive the logic to compute the next-state and output values. Show Karnaugh maps for the next-state variables and output variables and a gate-level schematic for the FSM.

14.8Modified traffic-light controller, II-III. Write and verify the VHDL that implements your state machine from Exercise 14.6.

14.9Modified traffic-light controller, III-I. Modify the traffic-light controller FSM of Table 14.4 so that the FSM stays in state GEW as long as carew is true. Show a state table and state diagram for your new FSM.

14.10Modified traffic-light controller, III-II. Choose a state assignment for the modified traffic-light controller of Exercise 14.9 and derive the logic to compute the next-state and output values. Show Karnaugh maps for the next-state variables and output variables and a gate-level schematic for the FSM.

14.11Modified traffic-light controller, III-III. Write and verify the VHDL that implements your state machine from Exercise 14.9.

14.12Modified pulse filler I. Modify the FSM of Example 14.1 so that it expects pulses on input a every six cycles, rather than five. Draw the state diagram for your modified FSM.

14.13Pulse-filler state table. Write a state table for the FSM of Example 14.1.

14.14Pulse-filler state assignment. Design a state assignment for the pulse-filler FSM of Example 14.1 using three state variables. The R state should have the encoding 000, and state 1 should have the encoding 001. Assign the remaining states so that as few state bits as possible change on each transition.

14.15Pulse-filler implementation.

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