Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications by Taimur Rabuske & Jorge Fernandes

Author:Taimur Rabuske & Jorge Fernandes
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

The expression may be elaborated more intuitively as follows. The numerator represents the amount of charge in the system. The left-hand term of the numerator is the charge initially stored in the TH. The value of CTH is divided by two because the TH capacitances appear in series for differential signals. The summation on the right side of the numerator represents the charges from the capacitors in the array that are connected in each cycle. The factor converts the comparator results from the conventional binary form {0, 1} to . The denominator of the expression represents the total capacitance that is connected to the comparator inputs in a given cycle, and again CTH appears dividing by 2. An identical effect is noticed in the parasitic capacitances, which also appear in series when the differential voltage is evaluated.

The equation is valid for any cycle i including 0, that corresponds to the MSB decision cycle. In the particular case when i = 0, the two summations have upper limit equal to 0, which is lower than the lower limit (that is 1). By definition, this is an empty sum, or a sum with no summands, and equals zero. Therefore, for i = 0, all the summands disappear remaining (4.18).

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