Analog Design and Simulation Using OrCAD Capture and PSpice by Dennis Fitzpatrick

Author:Dennis Fitzpatrick
Language: eng
Format: epub
ISBN: 9780081025062
Publisher: Elsevier Ltd.
Published: 2017-11-29T16:00:00+00:00

16.4.5 IBIS Translator

IBIS 1.1 models are supported in 16.5 whereas 16.6 supports IBIS models up to version 5.0.

In 16.6, IBIS and Cadence proprietary Device Model Language (DML) files can be translated into PSpice library files in the Model Editor. The translated IBIS I/O buffers are defined as macromodels.

IBIS (Input Output Buffer Information Specific) models are mainly used to analyse the transmission of digital high speed signals between ICs where the transmitted medium, usually copper traces, are modelled as transmission lines. The input and output buffers of ICs are characterised by tables of measured Voltage/Current and Voltage/Time data to provide a representation of I/O buffer behaviour without disclosing any proprietary information regarding the internal implementation of the I/O buffers. IBIS models based on these V/I and V/T tables can be used to analyse the Signal Integrity of the transmission of data by predicting the circuit response to mismatched impedance lines, crosstalk from adjacent transmission lines, overshoot, undershoot, ground bounce and simultaneous switching of digital high speed signals.

IBIS models provide a relatively accurate simulation model as they take into account structures for ESD protection and inherent parasitics associated with die bonding to the IC package pins. Compared to standard SPICE models, IBIS simulations run faster and do not suffer from non-convergence issues.

DML files are used by the existing suite of high speed simulation Cadence software tools for high speed analysis.

The IBIS translator is in the Model Editor and can be accessed from the top tool bar.

Model > IBIS Translator

The IBIS translator is not available in the demo Lite CD.

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