All-in-One Electronics Guide: Your complete ultimate guide to understanding and utilizing electronics! by Cammen Chan

Author:Cammen Chan [Chan, Cammen]
Language: eng
Format: epub, pdf
Publisher: C & C Group of Companies LLC
Published: 2014-11-02T23:00:00+00:00

Darlington Pair

The Darlington pair configuration is a popular circuit. This circuit was invented by Mr. Sidney Darlington in 1953 when he worked at Bell Lab. It’s still used today in many modern ICs. Let’s use PNP devices, this time connected as Darlington shown in figure 4.71. This circuit is a differential amplifier using PNP as the input stage, NPN as active load. The Darlington pair provides two features in this circuit: 1) maximum current gain, and 2) input voltage conversion. On point 1, current is increased from Q1 to Q2 using the transistor beta rule as

follows: Assume transistors’ beta (β) are equal, Figure 4.71: PNP Darlington pair

Q1_IE = Q1_IB + Q1_IC:

Q2_IB = Q1_IE:

Q1_IE = Q1_IB X (1 + β):

β >> 1, Q1_IE = Q1_IB + (Q1_IB X β) = Q1_IB (1 + β)

Q2_IC = β X Q1_IB (1 + β)

Q2_IC = β X Q1_IB X β

Q2_IC = β2 X Q1_IB

This shows that output current IE (Q2_IE) is much larger than the input current (Q1_IB) by β2. For example, if Q1_IB = 10 uA, beta are all 100. Q2’s emitter current:

Q2_IE = 1002 X 10 uA = 100 mA, 10,000 times larger On point 2, the input voltage at the Q1 base is “lifted” up two VBEs at Q2’s emitter (Q2_VE). If the input is 2 V, VBE is 1 V, and Q2_VB is at (2 V + 1 V) = 3 V. Adding one more VBE gives 4 V at Q2’s emitter, keeping Q2 and Q3 out of saturation. This input voltage conversion is likely needed especially when the input voltage is relatively low. For designs that require low input voltage, the Darlington pair becomes an ideal choice as an input stage. Imagine using the same circuit without the Darlington in figure 4.72. With 1 V input at Q1 and 1 V VBE, emitter voltage at Q1 = 1 V + 1 V = 2 V. Q3 collector stands at 1 V from Q3’s VBE. VEC across Q1 is now 2 V – 1 V = 1 V. For a particular bipolar process, 1 V VEC may be too low, forcing Q1 into saturation. Saturation should be avoided at all costs because it takes time for the transistor to recover from saturation during switching, hurting timing performance.

Figure 4.72: PNP differential pair with low input voltages

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