CMOS Integrated Circuit Design for Wireless Power Transfer by Yan Lu & Wing-Hung Ki

Author:Yan Lu & Wing-Hung Ki
Language: eng
Format: epub
Publisher: Springer Singapore, Singapore

In the traditional reconfigurable rectifier shown in Fig. 4.2, the output capacitors are connected in series which is not area-efficient for on-chip implementation. The effectiveness of utilizing on-chip capacitors in this design is significantly improved by the switching arrangement that avoids connecting the output capacitors in series in the 2X mode. Reverse current is reduced for |V AC| that ranges from 1.25 V to 4 V by the bias current that is quasi-inversely proportional to the output DC voltage V DC (QIPV).

Figure 4.28 shows the conventional and the proposed arrangement of CL. Assume that the total capacitance available is 4C for implementing CL, in the conventional topology, two 2C capacitors are connected in series that results in C L,EQ equal to C in both the 1X and the 2X mode. In the proposed topology, C FLY = C and C L = 3C are connected through switches S1 and S2. In the 1X mode, S1 is turned on, the two capacitors are in parallel, and C L,EQ is 4C; and in the 2X mode, S1 is opened, CFLY acts as a flying capacitor to charge up CL, and C L,EQ is 3C. As a result, the proposed topology increases C L,EQ by 4 and 3 times compared to the universal rectifier in the 1X and the 2X mode, making it possible to integrate the capacitors on-chip. In our case, C FLY and C L are equal to 1 and 3 nF respectively. Note that CFLY serves as a pumping capacitor for voltage doubling in a charge pump, and a small C FLY will limit the VCR and consequently the PCE. Based on the considerations of the VCR at the maximum loading condition in the 2X mode, C FLY is set to be 1 nF.

Fig. 4.28The conventional and the proposed arrangement of CL, assuming that the total capacitance available is 4C for implementing CL

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