Computer Architecture Tutorial Using an FPGA: ARM & Verilog Introductions by Robert Dunne

Author:Robert Dunne [Dunne, Robert]
Language: eng
Format: epub
Publisher: Gaul Communications
Published: 2020-08-22T23:00:00+00:00

Figure 12.6: Three formats of the second operand in every data processing instruction

Figure 12.6 shows how the immediate flag bits determine the format of the second operand..

SUB R1,R2 _____: All formats start with Rd and Rn.

Is the second operand an immediate constant (bit 25)?

SUB R1,R2, #4: Instruction with immediate constant

SUB R1,R2,R3, LSR __: Second operand is a register being shifted.

Is the shift count a constant (bit 4)?

SUB R1,R2,R3, LSR #17: Instruction with constant shift count

SUB R1,R2,R3, LSR R6: Instruction with shift count in register

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