Programming with STM32: Getting Started with the Nucleo Board and CC++ by Donald Norris

Author:Donald Norris
Language: eng
Format: epub
Publisher: McGraw-Hill Education LLC
Published: 2018-03-23T04:00:00+00:00

NVIC Specifications

The STM NVIC general specification states that up to 256 interrupt channels can be managed by a single NVIC. Out of the 256 channels, 240 may be external, while 16 are always internal. In reality, the NVIC portion of the STMF302R8 MCU, which controls the project development board, only supports 52 channels. In addition, there are 16 hardware interrupt lines that have direct connections to the NVIC. Any of the MCU’s 51 GPIO lines may be configured as a maskable interrupt, which means they can become an interrupt channel. You should think of an interrupt channel as more of a software construct than a hardware implementation. In fact, the interrupt C structure uses the word “channel” to reinforce this concept.

Interrupts also may be assigned a priority level. This means that a higher priority interrupt can interrupt a lower priority interrupt. This action gives meaning to the word “nested” in the acronym NVIC. An 8-bit register holds interrupt priority levels, which means there can be a maximum of 256 priority levels. I cannot conceive of a practical embedded system that would ever need anywhere that many interrupt priority levels. Such a system would likely be impossible to design, let alone implement.

It is time to now return to a detailed discussion of the interrupt process as I have already introduced the NVIC.

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