Emerging Technologies and Circuits by Amara Amara Thomas Ea & Marc Belleville

Author:Amara Amara, Thomas Ea & Marc Belleville
Language: eng
Format: epub
Publisher: Springer Netherlands, Dordrecht

Compared with LVDD, UVSS is much more efficient thanks to the reduction of ISTH of MAF transistor, as depicted in Fig. 8. Though, if the bit lines are left floating (FBL) the access transistor leakage are reduced by more than 1 decade becoming negligible and resulting in LVDD+FBL being as much efficient as UVSS+FBL. Those techniques give a total leakage current reduction around 80% for a delta of 0.4 V.

Fig. 8ISTH of MAF versus leakage reduction techniques at worst case (FF, 1.32 V, 125°C)

Figure 9 shows the SNM variations obtained for LVDD, UVSS, LVDD+FBL and UVSS+FBL leakage reduction techniques versus the delta voltage. The SNM measurements correspond to a read cycle following a long period of time in idle mode. The results have been normalized to the default SNM measured without leakage reduction techniques. Both UVSS and LVDD approaches degrade the SNM by up to 40%, UVSS representing the worst case. It originates from a lower r ratio. In order to have a SNM equal to or greater than the default one, FBL technique has to be added. The results show an improvement of 20%.

Fig. 9Normalized SNM (FS, 1.08 V, −40°C) versus the delta voltage applied to the ground or the supply voltage of the cell

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