CMOS Test and Evaluation by Manjul Bhushan & Mark B. Ketchen

Author:Manjul Bhushan & Mark B. Ketchen
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

In Fig. 6.8b, values of parameter p are mapped in gray scale across five selected chips numbered 1–5 on the wafer map in Fig. 6.8a. Dashed circles in the top left corner of each chip indicate locations of critical circuits. Because of the radial dependence at the edges of the wafer, the value of p in the critical area is different on each of the edge chips. Chips for detailed electrical characterization must be carefully selected after examining such data, as individual chips may have unique signatures.

In Fig. 6.9a, AcC variation of a single parameter is shown in shades of gray. Systematic variation of this type may be present in the photomask and hence repeated on every chip. At advanced technology nodes, sensitivity to local pattern density may also introduce such systematic variations across all chips. The chip in Fig. 6.9a has six identical critical circuit areas, such as cores in a microprocessor chip. If the parameter p affects circuit delays, these cores of identical design and physical layout may have different values of f max and V min. Another consequence of AcC variations indicated in Fig. 6.9a is that while chip f max is determined by the slowest core, the leakage current contributions of faster cores are disproportionately higher.

Fig. 6.9(a) Spatial variation of parameter p across a reticle field with six identical circuit blocks on the chip, and (b) variation of parameter p across chip and scribe-line (along dotted line)

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