Ageing of Integrated Circuits by Unknown

Author:Unknown
Language: eng
Format: epub
ISBN: 9783030237813
Publisher: Springer International Publishing

Error (%)

Selection set

Mean

−3σ

+3σ

S1

3.30

5.58

2.02

S2

4.98

8.39

2.23

S3

6.28

9.39

3.58

S4

8.01

11.43

4.88

S5

8.93

12.14

5.98

S6

10.83

13.77

8.12

S7

11.13

14.18

8.35

With a bit selection technique, the bit error rate varies depending on the selection window. For a proof of concept, the maximum error tolerance due to NBTI is set to be at 6%. Therefore, the selection set S1 is chosen and it is expected to reduce the area overhead of the ECC since the bit error rate is much smaller than without a bit selection technique (i.e. using all 32 bits). Nevertheless, other sources of variations that could cause errors in SUVs, in particular, temperature and supply voltage fluctuations must be considered in determining the complexity of ECC. According to [7], the maximum bit error is ≈6.2% for both selection sets, S1 and S7, caused by the temperature variations, in a range of −40 °C to 85 °C, and the supply voltage fluctuations of 1.2 V ± 10%. To be conservative, the maximum error tolerance is adjusted to be at 6.5% considering the ageing, temperature and supply voltage variations for S1 selection set.

The bit selection can be implemented using a multiplexer in which the select signals are preconfigured depending on the target error rate and bit select configuration. A 32-to-1 multiplexer is required to select 1 bit out of 32 bits from the output bus of the i-cache. Thus, the bit select block can be constructed using a 6 × 32-to-1 multiplexer for selecting the S1 bits: 16, 13, 25, 20, 12 and 23. In the procedure for cryptographic key generation shown in Fig. 4.6, the bit select block is inserted before the SUVs, and yˆ are input into the evaluation block (or can be inserted within the evaluation block). 280 GEs are required for a 6 × 32-to-1 multiplexer, estimated using Synopsys Design Compiler.

As discussed in Sect. 4.3.2, the BCH scheme is used as an ECC to generate error-free cryptographic keys. According to [3, 6], to ensure a sufficient entropy, an input to the hash function must be larger than the generated key. Therefore, the BCH scheme has to generate at least 171 error-free bits before being used as the input to the hash function to produce a 128-bit cryptographic key (Fig. 4.6). With the bit error rate of 6.5% and the target failure rate of ≤10−6, 1524 raw bits are required for the S1 selection set using a [127, 15, 27]-BCH [7]. Hence, the suggested minimum size of an i-cache to be used with the S1 selection is 1kB.

Without using a bit selection technique would require more area for the BCH scheme because of an increase in the bit error rates. Considering the bit error rates due to ageing and environmental variations, using all 32 bits would yield a maximum error of 14.18%. This requires 4599 raw bits using the BCH scheme of [511, 19, 119] for a target failure rate of ≤10−6 and a minimum i-cache size of 1 kB. The area for both BCH schemes earlier is estimated based on the extrapolated data of Fig. 4.12. Table 4.5 listed the comparison of area overhead with and without a bit selection technique.

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