Low Power Semiconductor Devices and Processes for Emerging Applications in Communications, Computing, and Sensing (Devices, Circuits, and Systems) by Sumeet Walia

Author:Sumeet Walia
Language: eng
Format: azw3, epub
Publisher: CRC Press
Published: 2018-08-12T16:00:00+00:00

7

Tunneling Field-Effect Transistors Based on Two-Dimensional Materials

Peng Zhou

CONTENTS

7.1 Introduction

7.2 The Principle of TFET

7.3 Performance Optimization

7.4 Feasibility of TFETs Based on 2D Materials

7.5 Current Status of TFETs Based on 2D Materials

7.6 Conclusion

References

7.1 Introduction

Although advanced complementary metal-oxide-semiconductors (CMOS) technology has achieved many extraordinary improvements in switching speed, density, functionality and cost, metal-oxide-semiconductor field-effect transistors (MOSFETs) are facing the challenges of scaling down the supply voltage with the increase in power density due to the thermionic emission limitation of carrier injection. Rising leakage currents degrade the I ON/I OFF ratio because the leakage currents will increase exponentially with a reduction in the supply voltage. Only the carriers in the exponential tail of the source Fermi distribution above the channel barrier can migrate to the channel. Considering a large enough bias, the drain current I d ∝ ∫ d E D ( E ) v ( E ) f s ( E ) , where D(E) is the density of states, v(E) is the carrier velocity and f s(E) is the source Fermi distribution. As D(E)v(E) is a constant for a specific product and f s(E) ≈ e E − E f s / k T , the SS can be obtained by

SS = ∂ V g ∂ ( log 10 I d ) = ∂ V g ∂ ( E q ) k T q ln 10 (7.1)

When considering all the gate voltage has been applied to the channel, we get the ideal case, SS = k T q ln 10 ,the minimal subthreshold swing of 60 mV/decade at room temperature, which can’t be overtaken even if scaled down. Although the power dissipation of a MOSFET, P = I OFF V DD 3 , the power consumption density increases sharply with the increase in I OFF when scaling down the supply voltage. The leakage power increases by 275-fold in commercial bulk CMOS 45 nm technology when lowering the supply voltage from 0.5 V to 0.25 V [1]. Therefore, it is necessary to resort to other physical mechanisms to solve the power consumption problem, like tunneling field-effect transistors (TFETs).

This review will concentrate on TFETs based on two-dimensional (2D) materials. The history of silicon TFET dates back to 1978 when Quinn et al. proposed the gated p-i-n structure [2], and it was experimentally realized in 1995 by Reddick and Amaratunga [3]. Lateral TFETs on silicon-on-insulator (SOI) observed negative conductance at 90 K [4] and TFETs on SOI with the gate overlapping the depletion region only to minimize capacitance [5]. Later, Group III-V materials [6] and nanotubes were used in TFET. Knoch and Appenzeller proposed nanotube TFETs and an experimentally realized SS below 60 mV/dec at room temperature for the first time in 2005 [7]. Vertical silicon TFETs were fabricated by Hansch et al. [8] using molecular beam epitaxy. TFETs achieved an SS below 60 mV/dec for the first time in a carbon nanotube field-effect transistor (FET) in 2004 [9]. Later, an average SS of ~25 mV/dec was achieved in a GaSb/InAs heterojunction [10] and ~7.8 mV/dec in an Si-based, arch-shaped, gate-all-around TFET [11].

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