But How Do It Know? - the Basic Principles of Computers for Everyone by J Clark Scott

Author:J Clark Scott [Scott, J Clark]
Language: eng
Format: epub
ISBN: 9780615303765
Amazon: 0615303765
Publisher: John C. Scott
Published: 2009-07-03T16:00:00+00:00

Below is the wiring within the Control Section that does the ‘fetch’ part of the instruction cycle. It uses the first three steps of the stepper and is the same for all types of instructions.

The stepper’s first three steps are shown here, and result in ‘fetching’ the next ‘instruction’ from RAM. Then the rest of the steps ‘execute’ the ‘instruction.’ Exactly what will be done in steps 4, 5 and 6, is determined by the contents of the instruction that was fetched. Then the stepper starts over, fetches the next instruction, and executes it.

The bottom of this diagram includes the Instruction Register. Notice that we have given numbers to the individual bits of the IR, 0 at the left through 7 on the right. We will be referring to the individual bits soon.

Here are the details of exactly how steps 1, 2 and 3 result in fetching an instruction in our little computer:

Step 1 is the most complicated because we actually accomplish two things at the same time. The main thing we want to do is to get the address in IAR over to MAR. This is the address of the next instruction that we want to fetch from RAM. If you look at the wire coming out of step 1 of the stepper, you can see that two of the places it is connected to are the ‘enable’ of IAR and the ‘set’ of MAR. Thus, the contents of IAR will be placed on the bus during ‘clk e’ and set into MAR during ‘clk s.’ Sometime during the instruction cycle, we need to add 1 to the value in IAR, and since IAR is already on the bus, we might as well do it now. If we don’t send anything to the ALU’s ‘op’ bits, they will all be zero, and since 000 is the code for ADD, the ALU will be doing an ADD operation on whatever is on its two inputs, and presenting the answer to ACC. One input comes from the bus, which has IAR on it during this time. If we also turn on the ‘bus 1’ bit during step 1, the other input to the ALU will be a byte with the binary value of 1. If we turn on the ‘set’ of ACC during ‘clk s,’ we will capture the sum of IAR plus 1 in ACC. This just happens to be the address of the instruction that we will want to fetch after we are done with the current one!

Step 2 enables the currently selected byte in RAM onto the bus, and sets it into IR. This is the instruction that we will ‘execute’ in steps 4, 5 and 6 of this instruction cycle. In the diagram, you can see that the wire coming from step 2 is connected to the ‘enable’ of RAM and the ‘set’ of IR.

In step 3, we need to finish updating IAR. We added 1 to it in step 1, but the answer is still in ACC.

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