Automated Analysis of Virtual Prototypes at the Electronic System Level by Mehran Goli & Rolf Drechsler

Author:Mehran Goli & Rolf Drechsler
Language: eng
Format: epub
ISBN: 9783030442828
Publisher: Springer International Publishing

FT3

Implementing an incorrect timing behavior can also cause an error. This is explicitly related to the timing annotation of a transaction and defined as the delay that the transaction requires to be transferred between two TLM modules. For example, the delay parameter of transactions generated by Initiator_A to access the address range (0x00 to 0x0A) of Memory_A must be less than 80 ns. Hence, designers want to know whether or not the timing behavior of the generated transactions by Initiator_A to access this range of address in Memory_A adheres the VP’s timing specifications. For this type of faults, again, traditional approaches such as [104] fail to validate the VP against its specifications.

Hence, to detect all the aforementioned types of fault, an automated validation process is required that not only checks the correctness of VPs against TLM-2.0 rules but also validates their functional and timing behavior against their specifications.

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