SystemVerilog for Hardware Description by Vaibbhav Taraate

Author:Vaibbhav Taraate
Language: eng
Format: epub
ISBN: 9789811544057
Publisher: Springer Singapore

module generated_clock(input a_in, b_in, clk, output logic clk_out);

logic tmp_clk;

always_ff @ (posedge clk)

begin : temp_clock

tmp_clk <= a_in;

end : temp_clock

always_ff @ (posedge tmp_clk)

begin : clock_output

clk_out <= b_in;

end : clock_output

endmodule

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The synthesis result is shown in Fig. 8.10, and the design uses the positive edge-triggered flip-flops. Such type of designs have the propagation delay of n*tpff where n = number of flip-flops and tpff = propagation delay of flip-flop.

Fig. 8.10Synthesis result for the generated clocks

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