Schaum's Outline of Computer Architecture by Carter Nick

Author:Carter, Nick [Carter, Nick]
Language: eng
Format: epub
Tags: Itzy, Kickass.to
ISBN: 007136207X
Amazon: 007136207X
Publisher: McGraw-Hill
Published: 2001-12-19T16:15:00+00:00

Solution

The pipeline latency of this processor is five cycles. Assuming that the LD issues on cycle n, the ADD cannot issue until cycle n + 2 because it is dependent on the LD. The SUB is independent of the ADD and the LD, so it also issues on cycle n + 2. (It cannot issue in cycle n or n + 1 because the processor must issue instructions in order.) The MUL is also independent of all previous instructions, but must wait until cycle n + 3 to issue, because the processor can only issue two instructions per cycle. Therefore, it takes four cycles to issue all of the instructions in the program, and the execution time is 5+4- 1 =8 cycles.

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