Quantum Computing for Computer Architects, Second Edition by Tzvetan S. Metodi & Arvin I. Faruque & Frederic T. Chong

Author:Tzvetan S. Metodi & Arvin I. Faruque & Frederic T. Chong
Language: eng
Format: epub
Publisher: Morgan & Claypool Publishers

Figure 6.2: High-level view of a specialized quantum architecture.

6.1 QUANTUM PROCESSING ELEMENTS (PE’S)

All logical quantum operations take place in the processing element (PE) tiles. A schematic of a hypothetical PE tile is shown in Figure 6.3. When a logical qubit is teleported to an available PE it is stored in either one of the two accumulators, and it is encoded with the compute code (CC), where the CC is chosen to be fast and relatively inexpensive in the number of physical qubits needed for encoding and error correcting a single logical qubit. Error correction is performed before and after the application of a single logical gate on the data stored in any of the two accumulators, using the closer of the two ancillary blocks. The logical qubit may be found waiting in the quantum cache encoded with the same CC, or is teleported directly from the main memory if there is an available accumulator in some PE unit. A two qubit gate requires the use of both accumulators, since the physical qubits of each of the two participating logical qubits must interact with one another. There are enough CC ancilla provided to correct both logical qubits in each of the accumulators. In reality, the lines between the different regions in each PE are not as clear as drawn in Figure 6.3. For example, in the ion-trap technology, the execution of a two-qubit gate with the Steane [[7, 1, 3]] code will require 49 pairs of ions to be placed in the same trap. Thus, both accumulators can be constructed by having 49 traps that allow physical two-qubits gates to be executed.

Ancilla 1

Accumulator 1

Accumulator 2

Ancilla 2

Figure 6.3: Hypothetical schematic of a Processing Element (PE) tile.

Gates acting on logical qubits must preserve fault-tolerance, so that a single error on any of the lower-level logical qubits will not spread to more lower-level qubits than the CC can correct. The gates act on logical qubits without decoding the states, thus a compiler optimizing the fault-tolerant structure of each gate must have clearly defined transformation rules that preserve fault-tolerance. The best CC’s are ones that: 1) Use very little physical qubit resource overhead; and 2) Allow “easy” fault-tolerant gate implementation. Good candidates for CC codes are the Steane [[7, 1, 3]] code, or the newly optimized Bacon-Shor [[9, 1, 3]] code [7, 11, 164]. The Bacon-Shor [[9, 1, 3]] code is based on the well known Shor 9-bit code [185] and allows very fast and efficient error correction routines. However, as shown in Section 4.2.3, the T gate is more difficult to implement. It requires the interaction of the logical qubit with a specially prepared encoded Aπ/8 ancilla (also in CC), making the T gate essentially a two-qubit gate [87]. Many of the tiles in the processing region must be used to prepare the Aπ/8 logical qubits; Thus, when a T gate is executed the logical qubit and a ready Aπ/8 qubit are teleported to two accumulators in an empty PE.

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