Programming FPGAs: Getting Started with Verilog by Monk Simon

Author:Monk, Simon [Monk, Simon]
Language: eng
Format: epub
Publisher: McGraw-Hill Education
Published: 2016-11-11T05:00:00+00:00

The 2-bit digit_posn counter will automatically wrap around from 3 to 0, and so does not need to be explicitly reset. The Elbert 2 has only three digits, so the digit_posn counter will need to be reset to 0 after the third digit has been displayed.

Counter_7_seg

The counter_7_seg module is the top-level module that pulls everything together. The module’s parameters are all concerned with GPIO pins and will map onto the nets defined in the UCF file. Here is the listing for counter_7_seg.v together with explanations of the code:

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