Programming FPGAs: A Practical Guide by Yury Magda & Yury Magda

Author:Yury Magda & Yury Magda [Magda, Yury]
Language: eng
Format: azw3
Published: 2017-03-16T04:00:00+00:00

Fig.53

In this circuit, we define the input/output ports and internal nets that will be used in the SystemVerilog code that follows.

This circuit comprises a frequency divider that provides the output signal with the frequency of 1 Hz (internal net clk) to the up/down counter. The frequency divider is fed by the 50 MHz clock source that arrives at the input port CLK_50M (pin 91).

The up/down counter is controlled through its three inputs, en, up/down and reset.

The up/down input of the counter is driven by the Q output of the S-R flip-flop (net dir in the SystemVerilog code). When dir = 1, the counter counts up to some predetermined value. Conversely, when dir = 0, the counter counts down to 0.

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