Post-Silicon Validation and Debug by Prabhat Mishra & Farimah Farahmandi

Author:Prabhat Mishra & Farimah Farahmandi
Language: eng
Format: epub
ISBN: 9783319981161
Publisher: Springer International Publishing

In the following section, all steps of the algorithm are reviewed by the aid of an example.

Fig. 10.3An example showing the different steps on choosing a suboptimal set of assertions to maximize flip-flop coverage is estimated

Example

The example in Fig. 10.3 will illustrate the process of assertion selection in each iteration in the proposed algorithm. Initially, the detection potential of each assertion is to be calculated according to formula in Eq. 10.1. Hence,

Note that and have been calculated based on the scaled values of Total Violation and Area. As it can be seen, the maximum detection potential is 1.04 and is associated with both assertion 1 and assertion 2. This is because both assertions have similar TotalViolation, FCov, WireCnt and Area. Referring to the ranking algorithm (Algorithm 1), the standard deviations for both assertions have to be calculated and their detection potential must be divided by the respective standard deviation. After the division, the assertion with highest DP is selected as the candidate assertion and the other one is dismissed from further evaluation. For our example, the DP values becomes

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