Low-Power VLSI Circuits and Systems by Ajit Pal

Author:Ajit Pal
Language: eng
Format: epub
Publisher: Springer India, New Delhi

Fig. 7.18Signal going from low-V dd to high-V dd domain causing a short-circuit current

High-to-Low-Voltage Level Converters

The need for a level converter as a signal passes from high-V dd domain to low-V dd domain arises primarily to provide a clean signal having a desired voltage swing and rise and fall times. Without a level converter, the voltage swing of the signal reaching the low-V dd domain is 0 to V ddH. This causes higher switching power dissipation and high leakage power dissipation due to GIDL effect. Moreover, because of the longer wire length between the voltage domains, the rise and fall time may be long leading to increase in short-circuit power dissipation. To overcome this problem, a level converter as shown in Fig. 7.19b may be inserted. The high-to-low level converter is essentially two inverter stages in cascade. It introduces a buffer delay and its impact on the static timing analysis is small.

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