Learning FPGAs: Digital Design for Beginners with Mojo and Lucid HDL by Justin Rajewski

Author:Justin Rajewski [Rajewski, Justin]
Language: eng
Format: azw3, pdf
Publisher: O'Reilly Media
Published: 2017-08-16T04:00:00+00:00

All the Channels

Now that we have one channel continuously sampling, we can make it a little more interesting by sampling all eight. To do this, we are going to use a counter that counts from 0–7. However, we have to modify the count value to generate the actual channel value. If the counter is greater than 1 (2–7), we will add 2 to it so it will count 0–1 then 4–9.

We need to increment the counter after we receive a sample for the currently selected channel. To do this, we need to convert the sample channel back to a counter value by subtracting 2 when the value is greater than 1.

To store these two intermediate values, we can use sig types:

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