Hot-Carrier Reliability of MOS VLSI Circuits by Sung-Mo (Steve) Kang & Yusuf Leblebici

Hot-Carrier Reliability of MOS VLSI Circuits by Sung-Mo (Steve) Kang & Yusuf Leblebici

Author:Sung-Mo (Steve) Kang & Yusuf Leblebici
Language: eng
Format: epub
Publisher: Springer-Verlag Wien 2012
Published: 2015-04-14T16:00:00+00:00


4.5.4. Model Implementation

For a given bias point, i.e., a set of terminal voltage values, the operating region of the MOS transistor must be determined first. Equation (4.18) provides an empirical approximation of the damaged MOSFET threshold voltage. If the gate-to-source voltage is less than the threshold voltage VTh, a conducting channel does not exist, i.e., the drain current is equal to zero. Once a conducting channel is established, one has to determine whether the transistor is operating in the linear region or in the saturation region. This can be accomplished by solving the single-variable nonlinear equation (4.20) for ΔL, by Newton-Raphson iteration. If the solution yields a positive depletion region length ΔL, the MOSFET is operating in the saturation region, and the saturation current can be found by solving equations (4.14) and (4.16) with Lef f = L − ΔL, as explained above. Otherwise, (4.14) and (4.16) are solved for the linear region drain current. It is seen that the implementation of the model equations given in Section 4.5 requires (i) the solution of a single-variable nonlinear equation by Newton-Raphson iteration, followed by (ii) the solution of two nonlinear equations with two unknowns. The computational cost associated with these steps has to be taken into consideration when using the model in circuit simulation tasks.

The simulated forward and reverse ID−VD characteristics of a damaged nMOS transistor are compared with measured data in Fig. 4.12. In this example, the channel length of the transistor is L = 1.7 µm, and the stress conditions are VD = 8 V, VG = 3 V, tstress = 5 × 104 s. It is seen that the proposed MOSFET model replicates the strong asymmetry between forward and reverse operation, which is due to the localization of oxide-interface damage near the drain. The uniform charge distribution model seen in Section 4.4 is not capable of reproducing this asymmetry which may seriously affect the performance of bidirectional devices such as transmission gates. On the other hand, the uniform model was found to provide satisfactory simulation results for the case in which both the source and drain ends of the channel are subjected to equal amounts of hot-carrier damage. Figure 4.12. Forward and reverse ID−VD characteristics of the nMOS transistor before and after hot-carrier stress. Stress conditions: VG = 3 V, VD = 8 V, tstress = 5 × 104 s. Channel length L = 1.7 µm [8].

○: Measured (forward and reverse) drain current before stress



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