HDL with Digital Design by Nazeih Botros

Author:Nazeih Botros [Nazeih Botros]
Language: eng
Format: epub, mobi
ISBN: 9781938549816
Publisher: Mercury Learning and Information
Published: 2015-02-09T05:00:00+00:00

pmos p1 (Qbar, s2, D);

pmos p2 (Qbar, s2, E);

pmos p3 (s2, vdd, Q);

pmos p4 (s2, vdd, Ebar);

endmodule

5.6.1.2 Switch-Level Logic Diagram of a D-Latch Using CMOS Switches

Figure 5.22 shows the switch-level logic diagram of the D-latch. When enable (E) is high, CMOS switch c1 is closed, CMOS switch c2 is opened, and Q follows D. When E is low, CMOS switch c1 is opened, CMOS switch c2 is closed, and Q retains its previous value.

Figure 5.22 Switch-level logic diagram of a D-latch using CMOS switches.

Listing 5.19 shows the HDL code for the D-latch. Due to the nature of signal Q, where it is an input and output with more than one source (one CMOS switch and an inverter), Q is declared as inout. Because there are three inverters, the inverter module discussed in Listing 5.3 is bound to the current module D-Latch, rather than writing three individual inverters. In VHDL, use the statement:

for all : invert use entity work.

inverter (Invert_switch);

to bind inverter to the current module D_Latch. In Verilog, we use the statement:

invert inv1 (Ebar, E);

which binds the module invert to the current module D_Latch.

Download

Copyright Disclaimer:
This site does not store any files on its server. We only index and link to content provided by other sites. Please contact the content providers to delete copyright contents if any and email us, we'll remove relevant links or contents immediately.