Getting Started with FPGAs by Russell Merrick

Author:Russell Merrick
Language: eng
Format: epub
Publisher: No Starch Press

Unexpected Timing Errors

You can fix most timing errors by pipelining your design to cut down on propagation delay and avoid metastable conditions. However, place and route tools can’t anticipate every timing error. These tools aren’t perfect; they can only analyze your design based on the information they have. Even if you don’t see any errors in your timing report, there are two situations where metastable conditions may still occur that the place and route tool can’t reliably predict:

When sampling a signal asynchronous to the FPGA clock

When crossing clock domains

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