FPGA Prototyping by Systemverilog Examples by Chu Pong P

FPGA Prototyping by Systemverilog Examples by Chu Pong P

Author:Chu, Pong P.
Language: eng
Format: epub
ISBN: 9781119282709
Publisher: Wiley
Published: 2018-05-03T16:00:00+00:00


The address translation circuit decodes the MCS I/O bus’s 32-bit byte address and converts it to the FPro bus’s 21-bit word address and chip-select signals. From MCS processor’s perspective, the FPro I/O system is a single I/O module with a 24-bit byte addressable space (i.e., 22-bit word addressable space) at a base address of 0xc0000000. The address translation circuit decodes the 32-bit address as follows:

bits 31 to 24: used to decode the FPro I/O module base address.

bit 23: used to distinguish the two subsystems and generate the chip-select signals.

bits 22 to 2: used to identify an I/O register or a memory location in the MMIO and video subsystems. They form the 21-bit FPro address.

bits 1 to 0: not used because FPro system uses “word address.”



Download



Copyright Disclaimer:
This site does not store any files on its server. We only index and link to content provided by other sites. Please contact the content providers to delete copyright contents if any and email us, we'll remove relevant links or contents immediately.