Embedded Systems Design with FPGAs by Peter Athanas Dionisios Pnevmatikatos & Nicolas Sklavos

Author:Peter Athanas, Dionisios Pnevmatikatos & Nicolas Sklavos
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

(1)

When X i  = 1 it means that the ith request has the highest priority to win a grant. Therefore, the grant signal G i is asserted when both X i and R i are equal to 1:

(2)

The search for the winning position should be performed in a circular manner after all positions are examined. Therefore, in order to guarantee the cyclic transfer of the priority, signal X N − 1 out of the most significant position should be fed back as a carry input to position 0, i.e., . Of course, we cannot connect X N − 1 directly to position 0 since this creates a combinational loop. In [9], an alternative fast circuit has been proposed that avoids the combinational loop and computes all X bits in parallel using the butterfly-like CLA structure shown in Fig. 11. Similar circuits can be derived after mapping on the FPGA the simplified and fully unrolled equations that describe the computation of the priority transfer signal X i :

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