Digital Logic Design and Computer Organization with Computer Architecture for Security by Faroughi Nikrouz

Author:Faroughi, Nikrouz
Language: eng
Format: epub, azw3
Publisher: McGraw-Hill Education
Published: 2014-09-10T16:00:00+00:00

Simulation Result:

As expected, the memory data lines indicated as data become high impedance (Z) when memory is not accessed.

References

1. Flash Memory: An Overview, http://www.spansion.com/Support/TechnicalDocuments/Pages/TechnicalDocuments.aspx.

2. C. R. Nave, HyperPhysics, Georgia State University, http://hyperphysics.phy-astr.gsu.edu/.

3. Memory chips from Micron, http://www.micron.com/products/dram/.

4. Memory from Rambus, http://www.rambus.com/.

5. Memory modules, http://www.newegg.com/.

6. Gomony MD, Akesson B, Goossens K. Architecture and optimal configuration of a real-time multi-channel memory controller, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 1307–1312.

7. Siqueira HM, Silva IS, Kreutz ME, Correa EF. DDR SDRAM memory controller for digital TV decoders, Symposium on Computing System Engineering (SBESC), 2011, 78–82.

8. NUMA SGI Altix 4700 system, http://www.sgi.com/products/.

9. AMD Quad FX Platform, http://support.amd.com/.

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