Cyber Physical Systems. Model-Based Design by Roger Chamberlain & Martin Edin Grimheden & Walid Taha

Author:Roger Chamberlain & Martin Edin Grimheden & Walid Taha
Language: eng
Format: epub
ISBN: 9783030411312
Publisher: Springer International Publishing

4 Empirical Analysis for Deriving a Practical Approach for Multicore Simulator

To minimize the inter-core interferences at the shared memory of multicore systems, the isolation techniques such as shared cache partitioning [12], memory bandwidth partitioning [21] and DRAM bank partitioning [20]. However, implementing those techniques on the PC is very complex requiring OS kernel modifications and even hardware changes.

Instead, focusing on automotive system tasks, we aim at finding a practical approach that can be easily implemented on the PC to prevent unpredictable inter-core interferences at the shared memory and hence make the existence of the execution time mapping functions valid even in the multicore environment. Since the automotive system tasks run on ECU which has limited memory resource, they are normally implemented to access the small memory section. For example, Fig. 5 shows the such small memory usages ranging from 1 KB to 35 KB of the automotive functions composing the body control module of Renault (Due to the confidentiality reasons, the specific information of each function is not given). If they are compiled on the simulation PC, we can expect the similar amount of memory footprint although the ISAs (Instruction Set Architectures) of PC and ECU are different. Thus, if a set of such small memory footprint tasks can reside within the per-core local cache which has 256 KB size in most modern general-purpose PC, after the cold starts at their initial executions, their accessed memory blocks will be copied to the local cache of each core and rarely evicted. Thus, they rarely access the shared memory and hence their execution times may not be severely affected by shared memory accesses from other cores.

In order to justify this conjecture, we make a synthetic task denoted by that accesses to an integer array in sequential order and calculate the sum of element-wide power. We use such a synthetic task since we can freely control its memory footprint size and its computation amount by controlling the array size. As a multicore simulation PC, we use a i7-3610QM [6] 4 core equipped Intel CPU which has a 256 KB local cache for each core and a 6 MB shared LLC. To obtain the base execution time of denoted by , we run it 5000 times exclusively on a single core keeping all other cores idle. Our experiments say that from the second to the 5000th execution times except the cold start execution, that is, the first one, are almost the same. Thus, we use their average as .

In order to investigate how much ’s execution time is affected by the inter-core interferences, we now concurrently run one denoted by on core-1 and the other s denoted by on core-2 and core-3 as changing their array sizes. In this experiment, the measured execution time of is denoted by . Figure 6 plots the normalized execution time of , i.e., . As increasing the size of , the normalized execution time of tends to increase. Such increase becomes sharper when is larger. This is because

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