Beginning FPGA: Programming Metal by Aiken Pang & Peter Membrey

Author:Aiken Pang & Peter Membrey
Language: eng
Format: epub
Publisher: Apress, Berkeley, CA

Tip

The bigger the counter size, the bigger the challenge for Quartus to compile it. 64-bit counters are still okay for the current FPGAs, but although Quartus may build a 256-bit counter, it’s unlikely that once in hardware it will be able to operate correctly.

library ieee; -- All of the deisgn need ieee library

use ieee.std_logic_1164.all; -- Using std_logic_1164 package

use ieee.numeric_std.all; -- Using numeric_std package

entity counter_4bit is

port (

CLOCK : in std_logic;

RESET : in std_logic;

ENABLE : in std_logic;

COUNTER : out std_logic_vector(3 downto 0) -- 4 bit counter output

);

end counter_4bit;

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