Assembly Language Coding in Color: ARM and NEON by Robert Dunne

Author:Robert Dunne [Dunne, Robert]
Language: eng
Format: azw3
Publisher: 9780970112439
Published: 2017-10-29T04:00:00+00:00

bits name Contents

31..28 Cond Only execute this instruction on condition of the value in the NZCF flags

27..26 00 These two bits are always zero for the data processing instruction type

25 # Immediate operand flag

24..21 Opcode Which operation (add, sub, and, orr, eor, …)

20 S Indicates that this instruction will modify the condition codes

19..16 Rn ID number of register containing the minuend (first operand)

15..12 Rd ID number of register to receive the result

11..0 op2 Three formats possible for second operand

Table 6.3: General bit layout for ARM data processing instructions (mov, add, sub, and, orr, eor, …)

Let’s continue to use the same subtraction example but include conditional assembly which is available in the 32-bit ARM instruction format. As before, we will subtract 7 from the contents of register R6, and store the result into register R5. However, in this example with the full power of the 32-bit ARM format, this instruction is only to be executed if the Z-flag is set, and its execution will set the NZCV flags depending on its result.

The assembler constructs the machine code instruction 0x02565007 by “filling in” the fields of the instruction word with “sub” = 0010, “eq” = 0000, “s” = 1, and “#” = 1. The operands and destination register ID are in the lower 20 bits of the instruction and consist of R5, R6, and the immediate constant of 7 as shown in the figure.

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