Artificial Intelligence Hardware Design by unknow

Author:unknow
Language: eng
Format: epub
Publisher: John Wiley & Sons, Incorporated
Published: 2021-08-18T00:00:00+00:00

Figure 5.1 Deep convolutional neural network hardware architecture.

The control commands are stored in external memory. They are loaded into a 128‐depth command FIFO to enable the accelerator. The commands are divided into configuration and execution commands. The configuration commands configure the network layer and enable pooling and ReLU functions. The execution commands initialize the convolution/pooling and instruct how to decompose the filter (Figure 5.2).

Figure 5.2 Convolution computation.

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