Algorithms and Architectures for Cryptography and Source Coding in Non-Volatile Flash Memories by Malek Safieh

Author:Malek Safieh
Language: eng
Format: epub, pdf
ISBN: 9783658344597
Publisher: Springer Fachmedien Wiesbaden

5.3 Implementation Results

In this section, we present implementation results for the proposed architectures. All results are provided for the Xilinx Virtex 7 FPGA.

All required resources are presented in Table 5.3, which is divided into three parts. In the upper part, we illustrate results for the proposed processor that utilizes modular arithmetic over ordinary prime fields, where we focus on the Solinas prime and arbitrary primes up to 192-bit. In the middle part, results for architecture that supports Montgomery arithmetic over Gaussian integers with different bit lengths are summarized. The lower part contains results from the literature for comparison. The parameter r denotes the maximum supported bit length (key length). The hardware requirements are represented by the number of LUT, FF, slices, and DSP units, as well as the RAM size. The maximum clock frequency is denoted by . Note that the look-up tables and slices provided by different FPGA devices vary, and hence they cannot be consistently compared. However, we can compare the number of registers required and the memory size with implementation on different FPGA devices from the literature.

All proposed processors were synthesized with and without the FPGA’s DSP units. However, the architectures were not optimized for the provided DSP units. The number of flip-flops is dominated by the registers of the arithmetic unit. The RAM size is the sum of the data and program memory sizes. For instance, a data memory with 38 words of m-bit and a program memory with 950 words of length 16-bit are sufficient for the processor that supports Gaussian integers, where m is determined according to (5.6). Consequently, the RAM requirements are dominated by the program memory. This is due to the fact, given that the arithmetic unit of both architectures performs only very simple operations and multiple instructions are required to perform a complete arithmetic operation of length r-bit.

The last column in Table 5.3 (denoted by flexible) indicates whether an implementation supports arbitrary prime fields (primes), different key representations (key expa.), or only prime curves that are proposed in [16] (fixed primes). Both proposed architectures are suitable for arbitrary primes up to length r-bit.

Similarly, Table 5.4 lists the PM latencies for the proposed processors in the upper and middle parts, respectively. Latencies for architectures from the literature are depicted in the lower part for comparison. The implementation of the architecture that supports prime field arithmetic results in the same operating frequency with and without DSP units, as shown in the first two rows of Table 5.3. For Solinas primes , the number of modular multiplications executed is significantly reduced compared with the Montgomery arithmetic. This results in reduced PM latencies, as illustrated in the first two rows of Table 5.4. This processor supports point multiplication only with binary key expansion. To protect the binary PM against SPA and timing attacks, we balance the number of applied DBL and ADD operations. The corresponding latencies are denoted by protected in Table 5.3. The results denoted by unprotected correspond to the PM with the minimum number of ADD and DBL operations.

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