A Practical Guide to Verilog-A by Unknown

Author:Unknown
Language: eng
Format: epub
Published: 2022-09-14T00:00:00+00:00

Chapter 8 BranChes

// 4 added to previously-retained 3

V(p,n) <+ 4.0;

end

endmodule

The value retention rules specify that the preceding example will result in an assignment of 7.0 to the potential signal of the unnamed branch between ports p and n.

Switch Branches

Contribution to a branch may be switched between a potential and a flow during a simulation. To this end, contribution statements are allowed within conditional statements as shown in the example:

module relay (p, n, ps, pn);

inout ps, ns;

output p, n;

electrical p, n;

parameter real thresh=0;

parameter real ron=0 from [0:inf);

parameter real goff=0 from [0:1/ron);

analog

if (V(ps,ns) > thresh)

V(p,n) <+ ron * I(p,n);

else

I(p,n) <+ goff * V(p,n);

endmodule

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Chapter 8 BranChes

Using the switch branch between ports p and n, the module relay

could represent also an ideal relay having zero on-resistance and zero off-conductance, set here as default.

The signals are contributed to switch branches using value retention rules. However, the switch branch expressions shall not use analog

operators if the condition can change during a simulation. A discontinuity in the first derivative of signal values is implicitly assumed to occur when the branch switches and it is not necessary to explicitly announce it with the $discontinuity system task. The use of the $discontinuity system task is described in Chapter 16.

If a conditional contributed statement branch is not executed for any particular iteration, and it is not a probe branch, it shall be treated as a flow branch with a value of 0. For example, the conditional contribution: if (closed)

V(p,n) <+ 0;

is equivalent to

if (closed)

V(p,n) <+ 0;

else

I(p,n) <+ 0;

Conversely, if a flow is contributed to a branch in some iterations

(when the condition is satisfied), and in other iterations, nothing is contributed, the branch is considered a potential branch with a value of 0.

In the following example of a resistor module, a switch branch is

controlled with the runtime constant condition:

module resistor(a, b);

inout a, b;

electrical a, b;

parameter real r = 1.0 from (0:inf);

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Chapter 8 BranChes

analog begin

if (r / $mfactor < 1.0e-3)

V(a,b) <+ 0.0;

else

I(a,b) <+ V(a,b) / r;

end

endmodule

The switch branch is not switching during iterations. It will be either a potential or a flow branch based on the value of the effective resistance r/$mfactor evaluated in the elaboration phase. In the case that the voltage branch is selected, the resistance is simply shorted out, and the simulator may collapse the node to reduce the size of the system of equations.

134

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