A Practical Approach to VLSI System on Chip (SoC) Design by Veena S. Chakravarthi

Author:Veena S. Chakravarthi
Language: eng
Format: epub
ISBN: 9783030230494
Publisher: Springer International Publishing

Programmable memory BIST (MBIST) insertion is the process in which memory BIST logic is inserted that allows for control, testing, and diagnostics of the memory cell instances via IEEE 1149.1 or 1149.6 JTAG control or direct pin access control. Programmable memory BIST logic permits memory cells in the SOC independently from system modes. Insertion of the PMBIST logic is customized for each design using a configuration file.

7.8 Power Aware Test Module Insertion (PATM)

PATM insertion inserts overriding control logic into the design’s power-manager control block(s) in order to stabilize the power-manager control pins to the switchable power domains during test. PATM logic is inserted into the design’s power-manager control block(s) for the power domains defined in UPF file. These are used to generate patterns for self-testing. This reduces the dependence on external automated test equipment (ATE).

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